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Freescale MPC5634M 32位MCU开发方案

时间:2015-08-24  来源:扁平线圈电感厂家  点击:
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— Deserial serial interface (DSI)

– Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO

– 32 bits per DSPI module

– Triggered transfer control and change in data transfer control (for reduced EMI)

– Compatible with Microsecond Channel Version 1.0 downstream

• Two enhanced serial communication interface (eSCI) modules

— UART mode provides NRZ format and half or full duplex interface

— eSCI bit rate up to 1 Mbps

— Advanced error detection, and optional parity generation and detection

— Word length programmable as 8, 9, 12 or 13 bits

— Separately enabled transmitter and receiver

— LIN support

— DMA support

— Interrupt request support

— Programmable clock source: system clock or oscillator clock

— Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0

• Two FlexCAN

— One with 32 message buffers; the second with 64 message buffers

— Full implementation of the CAN protocol specification, Version 2.0B

— Based on and including all existing features of the Freescale TouCAN module

— Programmable acceptance filters

— Short latency time for high priority transmit messages

— Arbitration scheme according to message ID or message buffer number

— Listen only mode capabilities

— Programmable clock source: system clock or oscillator clock

— Message buffers may be configured as mailboxes or as FIFO

• Nexus port controller (NPC)

— Per IEEE-ISTO 5001-2003

— Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1

— Read and write access (Nexus class 3 feature that is supported on this device)

– Run-time access of entire memory map

– Calibration

— Support for data value breakpoints / watchpoints

– Run-time access of entire memory map

– Calibration Table constants calibrated using MMU and internal and external RAM
Scalar constants calibrated using cache line locking

— Configured via the IEEE 1149.1 (JTAG) port

• IEEE 1149.1 JTAG controller (JTAGC)

— IEEE 1149.1-2001 Test Access Port (TAP) interface

— 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions

— 5-bit instruction register that supports additional public instructions

— Three test data registers: a bypass register, a boundary scan register, and a device identification register

— Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled until the next reset

— TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry

• On-chip Voltage Regulator for single 5 V supply operation

— On-chip regulator 5 V to 3.3 V for internal supplies

— On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic

• Low-power modes

— SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the PLL) selectively disabled in software

— STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system clock after a predetermined time

图1.MPC5634M 系列方框图

MPC5634M 系列应用:

Gasoline Engine Managemen...

Motorcycle Engine Control...

Integrated Small Engine C...

Hybrid Electric Vehicle (...

Advanced Heat Meter

Low-End Mechanical Type w...

Controller Area Network (...

Diesel Engine Management

Basic Heat Meter

Thermostat

TRK-MPC5634M低成本开发系统

The TRK-MPC5634M is a low-cost development system supporting Freescale MPC5634M microcontrollers in 144LQFP packages. The Embedded OSJTAG circuitry on the TRK-MPC5634M board allows the processor on the board to be debugged and programmed via USB from a PC.

In addition, the demo board can be powered using the USB bus.

The TRK-MPC5634M package includes the following items:

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