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Freescale MPC5634M 32位MCU开发方案

时间:2015-08-24  来源:扁平线圈电感厂家  点击:

Freescale 公司的MPC5634M是基于Power Architecture®的32位MCU,用户模式100%和Power Architecture 指令集兼容,工作频率0 MHz-80 MHz ,工作温度到+150度C,具有低功耗性能,工作电压4.5 V-5.25 V,内部稳压器提供3.3V和1.2V用于内核和逻辑电路,主要用于气油引擎管理,摩托车引擎控制,混合动力汽车,热量表和温度控制器,CAN等.本文介绍了MPC5634M主要特性,框图,TRK-MPC5634M低成本开发系统主要特性,电路图和PCB元件布局图.

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5634M series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5634M Microcontroller Reference Manual.

The MPC5634M series microcontrollers are system-on-chip devices that are built on Power Architecture® technology and:

• Are 100% user-mode compatible with the Power Architecture instruction set

• Contain enhancements that improve the architecture’s fit in embedded applications

• Include additional instruction support for digital signal processing (DSP)

• Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter,

Controller Area Network, and an enhanced modular input-output system

MPC5634M主要特性:

• Operating Parameters

— Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)

— –40 degreeC to 150 degreeC junction temperature operating range

— Low power design

– Less than 400 mW power dissipation (nominal)

– Designed for dynamic power management of core and peripherals

– Software controlled clock gating of peripherals

– Low power stop mode, with all clocks stopped

— Fabricated in 90 nm process

— 1.2 V internal logic

— Single power supply with 5.0 V -10%/+5% (4.5 V to 5.25 V) with internal regulator to provide 3.3 V and 1.2 V for the core

— Input and output pins with 5.0 V -10%/+5% (4.5 V to 5.25 V) range

– 35%/65% VDDE CMOS switch levels (with hysteresis)

– Selectable hysteresis

– Selectable slew rate control

— Nexus pins powered by 3.3 V supply

— Designed with EMI reduction techniques

– Phase-locked loop

– Frequency modulation of system clock frequency

– On-chip bypass capacitance

– Selectable slew rate and drive strength

• High performance e200z335 core processor

— 32-bit Power Architecture Book E programmer’s model

— Variable Length Encoding Enhancements

– Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions

– Results in smaller code size

— Single issue, 32-bit Power Architecture technology compliant CPU

— In-order execution and retirement

— Precise exception handling

— Branch processing unit

– Dedicated branch address calculation adder

– Branch acceleration using Branch Lookahead Instruction Buffer

— Load/store unit

– One-cycle load latency

– Fully pipelined

– Big and Little Endian support

– Misaligned access support

– Zero load-to-use pipeline bubbles

— Thirty-two 64-bit general purpose registers (GPRs)

— Memory management unit (MMU) with 16-entry fully-associative translation look-aside buffer (TLB)

— Separate instruction bus and load/store bus

— Vectored interrupt support

— Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt exception handler)

— Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g., power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be recoverable)

— Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt Controller. (Always recoverable)

— New ‘Wait for Interrupt’ instruction, to be used with new low power modes

— Reservation instructions for implementing read-modify-write accesses

— Signal processing extension (SPE) APU

– Operating on all 32 GPRs that are all extended to 64 bits wide

– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including integer vector MAC and MUL operations) (SIMD)

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