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Freescale MPC5634M 32位MCU开发方案

时间:2015-08-24  来源:扁平线圈电感厂家  点击:


• System integration unit (SIU)

— Centralized GPIO control of 80 I/O pins

— Centralized pad control on a per-pin basis

– Pin function selection

– Configurable weak pull-up or pull-down

– Drive strength

– Slew rate

– Hysteresis

— System reset monitoring and generation

— External interrupt inputs, filtering and control

— Critical Interrupt control

— Non-Maskable Interrupt control

— Internal multiplexer subblock (IMUX)

– Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)

– Allows selection of interrupt requests between external pins and DSPI

• Error correction status module (ECSM)

— Configurable error-correcting codes (ECC) reporting

— Single-bit error correction reporting

• On-chip flash memory

— Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface

— 16 KB shadow block

— Fetch Accelerator

– Provide single cycle flash access at 80 MHz

– Quadruple 128-bit wide prefetch/burst buffers

– Prefetch buffers can be configured to prefetch code or data or both

— Censorship protection scheme to prevent flash content visibility

— Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other array (used for EEPROM emulation)

— Memory block:

– For MPC5634M: 18 blocks (4 x16 KB, 2 x32 KB, 2 x64 KB, 10 x128 KB)

– For MPC5633M: 14 blocks (4 x16 KB, 2 x32 KB, 2 x64 KB, 6 x128 KB)

– For MPC5632M: 12 blocks (4 x16 KB, 2 x32 KB, 2 x64 KB, 4 x128 KB)

— Hardware programming state machine

• On-chip static RAM

— For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply

— For MPC5633M: 64 KB general purpose RAM of which 32 KB are on standby power supply

— For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply

• Boot assist module (BAM)

— Enables and manages the transition of MCU from reset to user code execution in the following configurations:

– Execution from internal flash memory

– Execution from external memory on the calibration bus

– Download and execution of code via FlexCAN or eSCI

• Periodic interrupt timer (PIT)

— 32-bit wide down counter with automatic reload

— Four channels clocked by system clock

— One channel clocked by crystal clock

— Each channel can produce periodic software interrupt

— Each channel can produce periodic triggers for eQADC queue triggering

— One channel out of the five can be used as wake-up timer to wake device from low power stop mode

• System timer module (STM)

— 32-bit up counter with 8-bit prescaler

— Clocked from system clock

— Four-channel timer compare hardware

— Each channel can generate a unique interrupt request

— Designed to address AUTOSAR task monitor function

• Software watchdog timer (SWT)

— 32-bit timer

— Clock by system clock or crystal clock

— Can generate either system reset or non-maskable interrupt followed by system reset

— Enabled out of reset

• Enhanced modular I/O system (eMIOS)

— 16 timer channels (up to 14 channels in 144 LQFP)

— 24-bit timer resolution

— Supports a subset of the timer modes found in eMIOS on MPC5554

— 3 selectable time bases plus shared time or angle counter bus from eTPU2

— DMA and interrupt request support

— Motor control capability

• Second-generation enhanced time processor unit (eTPU2)

— Object-code compatible with eTPU—no changes are required to hardware or software if only eTPU features are used

— Intelligent co-processor designed for timing control

— High level tools, assembler and compiler available

&md电感器图片ash; 32 channels (each channel has dedicated I/O pin in all packages)

— 24-bit timer resolution

— 14 KB code memory and 3 KB data memory

— Double match and capture on all channels

— Angle clock hardware support

— Shared time or angle counter bus with eMIOS

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注塑加工厂


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